1. Technical Field of the Invention
The present invention relates to a static sense amplifier having feedback, particularly for non-volatile memories.
More particularly, the present invention relates to a feedback static sense amplifier for non-volatile memories such as EPROMs, EEPROMs and FLASH EEPROMs.
2. Background of the Relevant Art
In order to correctly read the data item from a memory cell from a memory matrix, it is known to compare the data item read from the memory matrix cell with the data item read from a reference matrix cell, so as to detect the difference between a programmed cell and a non-programmed cell.
For this purpose, memory matrices are usually preset so that a reading of the data item from a memory cell is matched by a reading of an amount of current that flows across a reference matrix cell. The differential between the two readings determines the particular data item read.
Referring to FIGS. 1 and 2, there is shown conventional memory read circuits including a reference branch, i.e., a reference bitline, designated by the reference numeral 1, and a corresponding bitline, designated by the reference numeral 2, which is the bitline to which the memory cells to be read are coupled.
The reference numeral 3 designates bitline selection devices, while the reference numeral 4 designates devices for biasing the bitlines, i.e., for precharging the bitlines.
The reference numeral 5 designates a sense amplifier circuit which is adapted to read the data of the memory cells by comparing the current that flows across the memory cell to be read with the current that flows across a corresponding reference cell.
The reference branch of the conventional read circuits includes transistors M1, M3, M7 and M9, while the memory cell branch of the conventional read circuits includes transistors M2, M4, M6 and M10, as shown in FIGS. 1 and 2.
A driving signal is sent to the gate terminals of the transistors M3 and M4 to charge the reference bitline 1 and the memory cell bitline 2. The signals sent to the transistors M3 and M4 are REF-CASC and CASC, respectively.
Further, a transistor M5 is connected so as to receive at its gate terminal the signal REF-CASC. The source terminal of transistor M5 is connected to the drain terminal of the transistor M3.
In a similar manner, transistor M6 is connected in the memory cell branch of the read circuit and receives the signal CASC at its gate terminal.
The sense amplifier 5 includes a differential amplifier 6 which receives the signals REFSIDE and MATSIDE at its noninverting and inverting terminals, respectfully. Signals REFSIDE and MATSIDE are signals taken from the reference branch and memory cell branch of the memory read circuitry, respectively. The output of the differential amplifier 6 is a signal DIFFOUT which drives a pair of series-connected inverters 7 and 8, the output of which is a signal designated DATA.
The function of the transistor M6 is to limit the oscillation of the node MATSIDE when the current that flows in the matrix side or memory cell branch of the memory read circuit, designated by Icell, is greater than the reference current Iref that flows in the reference side branch of the memory read circuit. This prevents the cascode device from entering the linear region, thereby maintaining the correct voltage level on the bitline 2.
Another important role of the transistor M6 is to shorten the recovery time of the node MATSIDE during the transient that follows the selection of the new bitline 2.
Specifically, when a column address changes, the previously selected bitline 2 is in fact deselected and a new bitline 2 (not shown) is connected to the input YMS of the sense amplifier 5. The selection and connection of the new bitline 2 (which is assumed not to be charged) causes the node YMS to fall from its existing operating level due to charge sharing with the high capacitive load of the new bitline 2. The amount of charge appearing on node MATSIDE also falls in response to the fall in charge appearing on the node YMS.
This fall in the amount of charge appearing on nodes YMS and MATSIDE is limited by the transistor M6. Directly after the selection of the new bitline 2 and corresponding drop in charge on nodes YMS and MATSIDE, the charge appearing thereon begins to rise.
During this charge transient, the current is supplied to nodes MATSIDE and YMS by the transistor M2 (whose current is constant because it is the reference current Iref mirrored by the transistor M1) and the transistor M6.
At this point, two possible situations must be considered.
First, consider the situation in which the current Icell that flows across the selected memory cell connected to bitline 2 is greater than the reference current Iref that flows across the corresponding reference cell connected to reference bitline 1 and is mirrored in transistor M2. In this case, the voltage appearing on node MATSIDE rises until the current that flows across the transistor M6 decreases. The current equation for node MATSIDE can be expressed as: EQU I(M6)=Icell-Iref,
where I(M6) is the current through transistor M6.
In this situation, the particular voltage level at which the node MATSIDE stabilizes is lower than the voltage level appearing on the node REFSIDE and depends on the control voltage of the gate terminal of the transistor M6.
In the circuit implementation shown in FIG. 1, the gate terminal of the transistor M6 is controlled, as mentioned, by the signal CASC, which is the same signal used to bias the bitline 2. On the other hand, in the conventional memory read circuit shown in FIG. 2, the transistor M6 is controlled by the node REFSIDE.
Since the operating voltage level of the node REFSIDE is greater than the voltage level appearing on the node CASC (the bitline biasing devices M3 and M4 work at saturation), the voltage level at which the node MATSIDE stabilizes in the circuit of FIG. 2 is greater than the corresponding voltage level of the node MATSIDE in the circuit of FIG. 1. FIGS. 4A and 4B illustrate the voltage characteristics of node MATSIDE during a portion of a memory read operation for the read circuits of FIGS. 1 and 2, respectively.
A second situation exists when the current Icell that flows across the selected memory cell is lower than the reference current Iref. In this situation, the operating point of the node MATSIDE is greater than the operating point of the node REFSIDE (the transistor M2 in this case enters the linear region). Before the node MATSIDE, during its recovery, reaches the node REFSIDE, the transistor M6 is shut off. The particular voltage level appearing on the node MATSIDE which results in the transistor M6 turning off depends on the signal used to control the gate terminal of transistor M6.
It should be noted that after the transistor M6 has switched to the off state, charging of the node MATSIDE becomes slower since it is charged only by the reference current Iref from transistor M2.
Accordingly, the circuit of FIG. 2 is more effective than the circuit of FIG. 1 in terms of the capability to provide faster recovery of the node MATSIDE. FIGS. 5a and 5b illustrate the recovery times for the read circuits of FIGS. 1 and 2, respectively.
The recovery time of the node MATSIDE can be considered as a critical time period for the speed performance of the sense amplifier 5 of a non-volatile memory.